Solution:

All interrupt inputs on PCL-833 are controlled and managed by two registers of on-board 8259 interrupt controller. The BASE+12 is mapped to ICW1, OCW2, or OCW3 which first bit (A0) is labeled as 0 on manual page 50-52. The BASE+13 is mapped to ICW2/3/4, or OCW1 which first bit (A0) is labeled as 1. After the Initialization Command Words (ICWs) are written into the 8259, the chip is ready to accept interrupt requests regarding its input lines. And, a selected algorithms control the Operation Command Words (OCWs) to let 8259 operating in various mode. Each interrupt requesting input can be masked individually by the Interrupt Mask Register (IMR) with OCW1. The 8259 mask register is at BASE+13 of PCL-833. Its relative bit for each interrupt are as follows : bit 0 --- counter1 overflow bit 1 --- counter2 overflow bit 2 --- counter3 overflow bit 3 --- counter1 index in (Zin) bit 4 --- counter2 index in bit 5 --- counter3 index in bit 6 --- DI0 input bit 7 --- DI1 input or Timer pulse (bits of BASE+9 selects DI1 or Timer) The demo program 833DEMO3.C needs to be change as below : base = 0x200; irqI = 2; slrscr(); // Initialization Command Word outportb(base+12,0x13); // ICW1 outportb(base+13,0x00); // 0x60 -> 0x00, ICW2 IRQ0 -> NO. 60-67 outportb(base+13,0x0b); // ICW4 // Operation Control Word outportb(base+13,0x77); // Enable counter 1 Zin interrupt and 1 sec. timer interrupt init_INT(); outportb(base+9, 0x0C); // select timer interrupt and 1654 time base outportb(base+10,0x01); // divide