Solution:

Internal Pacer Trigger Connection The PCI-1710/1710L/1710HG/1710HGL/1711/1711L/1716/1716L includes one 82C54 compatible programmable Timer/Counter chip which provides three 16-bit counters connected to a 10 MHz clock, each designated specifically as Counter 0, Counter 1 and Counter 2. Counter 0 is a counter which counts events from an input channel or outputing pulse. Counter 1 and Counter 2 are cascaded to create a 32-bit timer for pacer triggering. A low-to-high edge from the Counter 2 output (PACER_OUT) will trigger an A/D conversion on the PCI-1710/1710L/1710HG/1710HGL/1711/1711L/1716/1716L. At the same time, you can also use this signal as a synchronous signal for other applications. External Trigger Source Connection In addition to pacer triggering, the PCI-1710/1710L/1710HG/ 1710HGL/1711/1711L/1716/1716L also allows external triggering for A/D conversions. When a +5 V source is connected to TRG_GATE, the external trigger function is enabled. A low-to-high edge coming from EXT_TRG will trigger an A/D conversion on the PCI-1710/1710L/1710HG/1710HGL/1711/1711L/ 1716/1716L. When DGND is connected to TRG_GATE, the external trigger function is thereby disabled.